Hjdcti

I have a square output from an LM324 op-amp (0 and 5 volts) which has a frequency between 1 to 500 Hz (yes, low frequencies). I would like to find a simple way to have HIGH TTL signal when it is over 50 Hz and a LOW when it is below that. It's not necessary to be so precise, but around 50 Hz will be fine. I know that I can do it by uCs, and I did it. However I have 1500 outputs which I should make a network from, and I would like to make it cheap and fast.

More info about the signal: The frequency is almost fixed at something above 50, say 150Hz or may be 250Hz or so, and the frequency variation is less than 10 Hz, then suddenly it will drop to less than 50, stays for a minute and again back up.

Finally: Is there a way I can control this 50Hz threshold by uC?

One way to solve this problem is to use a re-triggerable one-shot component. You said that absolute tolerance is not super critical and so the typical tolerances of a one-shot may be a suitable and simple means to detect the frequency shift of your signal.

The one-shot needs to be setup with a R/C timing delay just at the timing period of your signal at 50Hz. This would be 20msec. As long as the input trigger signal at the one-shot stays above the 50Hz rate the output of the one-shot will stay re-triggered at a high level. When the input frequency drops below 50Hz the one-shot will start to timeout on each input pulse and its output will start to pulse with each cycle of the lower frequency input.

You could possibly use this as is depending upon what you are using to detect the frequency changes or you could add some additional simple logic to convert the lower frequency pulsing output of the one-shot to a static signal envelope. I'll leave that detail for you to figure out in the case you find this re-triggerable one-shot idea suitable to your application.

You have multiple alternatives, each one of them with different trade offs.

• The conceptually simplest and most precise one, would be to use a pulse counter.

This is probably what you implemented with your micro controller. Gate a known fast clock with each cycle of the input signal and compare that count to a reference.

• Translate that same idea to the analog domain. Using a ramp as the “counter”.

Start a known slew-rate ramp with an edge of the signal and capture the value on the next edge. Compare this value to a reference. Monolithic latching comparators make this simpler than it sounds.

• Use a retriggerable monostable. With the duration being the comparison value.

A retriggerable monostable with a period of 20ms will remain triggered as long as the signal is above 50Hz, and will generate pulses when it’s below that. A second retriggerable monostable can “filter” these pulses into a continuous signal.

• use a filter slope and a peak detector (just as some cheap FM radios)

A filter slope (high-pass or low-pass will do) attenuates different frequencies differently. By detecting the amplitude of the output signal you can compare to a threshold. The higher the filter slope the higher the frequency gain.

• use a known pulse size to convert to PWM. (Frequency to voltage conversion).

By triggering a known-size pulse with each signal edge (with a monostable or just an edge detector) you convert the signal to PWM whose DC average will be proportional to the frequency. You can then use an analog comparator to detect the transition.

Given that you are talking of thousands of signals, any analog solution might be difficult to use reliably with a desired tolerance. Besides, you will need multiple components for each channel; at least 1 IC and multiple passives.

If you simply program a 14-pin microcontroller to implement just this function on several channels, you can use 1 IC for 5 channels or so. With much better precision, reliability, and repeatability. Even a 6-pin micro at 1 IC per channel would be smaller and simpler.